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IEEE DTS Conference Chairs

Pr. Mohamed Masmoudi
National Engineering School of Sfax (ENIS) - Tunisia

Pr. Jaouhar Mouine
Prince Sattam bin Abdulaziz University (PSAU) - KSA


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February 28th, 2019

DTS’19 Workshops

Workshop 1

Challenges and Emerging Solutions in Testing Embedded IO interfaces in 2.5D and 3D Systems

Workshop Summary:
In response to the increasing challenges in maintaining technology advancements through traditional scaling at a pace consistent with or exceeding Moore's Law, alternative methods to achieve enhanced system level performance are becoming increasingly important. Three-dimensional integrated circuit (3D IC) and 2.5D IC with Si interposer are regarded as promising candidates to overcome the limitations of Moore’s law because of their advantages of lower power consumption, smaller form factor, higher performance, and higher function density. Systems using embedded DRAM interconnected via a high density substrate with interposer-like technologies or via Thru-Silicon Via (TSV) are being introduced in a broad array of products.

In this workshop we present testability methodology practices for 2.5D and 3D products with embedded IO interfaces. As opposed to conventional testing, 2.5D and 3D ICs test flows are more complex and new DFx methodologies will be presented that provide good coverage and visibility to isolate failures in High Volume Manufacturing.


Full name: Salem Abdennadher
Affiliation: Intel Corporation

Presenter Biography:
Salem Abdennadher, Principal Engineer, Intel Corporation has 20+ years of experience in mixed-signal design and DFT. Soon after graduating with Masters from Oregon State University 1992, he joined the industry and has worked with a research lab in Tunisia, Motorola, Level One Communications and Intel. His recent publications and international patent filing in mixed signal DFT/BIST ranges from Filter BIST, On-chip Jitter BIST, to mixed signal behavioral modeling and noise extraction and prediction. Salem also has presented dozens of tutorials through TTEP at ATS, LATW, VTS, ITC. Presented multiple Workshops, publication, Special sessions presentation in International test Conference, VLSI test Symposium. European Test Symposium, Latin test Workshop